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Espressif Systems /ESP32-S2 /SYSTEM /CPU_PER_CONF

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Interpret as CPU_PER_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CPUPERIOD_SEL 0 (PLL_FREQ_SEL)PLL_FREQ_SEL 0 (CPU_WAIT_MODE_FORCE_ON)CPU_WAIT_MODE_FORCE_ON 0CPU_WAITI_DELAY_NUM

Description

CPU peripheral clock configuration register

Fields

CPUPERIOD_SEL

This field is used to select the clock frequency of CPU or CPU period.
PLL_FREQ_SEL

This field is used to select the PLL clock frequency based on CPU period.
CPU_WAIT_MODE_FORCE_ON

Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction.
CPU_WAITI_DELAY_NUM

Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data